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(Solved): Write a VHDL code to describe the circuit completely. Do produce a timing chart with all possible c ...
Write a VHDL code to describe the circuit completely. Do produce a timing chart with all possible combinations of the input.
Use ModelSim to write:
• VHDL code (in text format so that I can test the code myself)
• Tested on a testbench (another VHDL),
• Then simulated in time, and draw (attach) the timing diagram showing all combinations.
FIGURE 12-1 4-Bit D Flip-Flop Registers with Data, Load, Clear, and Clock Inputs
Expert Answer
Solution-: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity multiplexer is port( a, b : in std_logic_vector(3 downto 0); sel : in std_logic; y : out std_logic_vector(3 downto 0) ); end multiplexer; architecture behavioral o