(Solved): Please write the state diagram in verilog using case statement. You can modify the verilog example t ...

Please write the state diagram in verilog using case statement. You can modify the verilog example to match the state diagrams or write a new one using case statement. Thank you.

Problem #3

State Diagram

 

Verilog example.

#3 Use Verilog to play a slot machine: Designate 3 square buttons A, B, C and a cricket button S to play it. S (re)starts the game, and A B C each picks a result to be displayed onto the 3 7-segment LED displays respectively. If all three picked match, you win, and an additional red dot appears onto the 7x5 LED matrix display. What is displayed when you push a A, B, or C can be blank, a single bar (lit up the middle of the 7-segment LED display), a double bar (lit up the upper and middle bars), or a treble bar (lit up the top, middle, and bottom bars). Use the internal clock to fast count, and whenever A, B, or C is pressed, take the current count and modulus 4 on it, and take the result as 0-blank, 1-single bar, 2=double bar, 3=treble bar. To make the game look more exciting, S makes all 3 displays go very fast until each is picked. Design a state-transition diagram using the notations from the State Machine Diagram (SMD) illustrated at the end of Chapter 5. The Slot Machine Problem faste ++ 'ST' Power on power on Rst count (fast_c) charp A pushed Rst Counters input power mastor clk fast C++ out put output: fast_c Rst Charl Bpushed Cpushed Rst Char 2 (554 83 charp=char/= char 2 win tt Chard=charl=char 2 charx = fast_cx. 4 input: Rst A B C Power (Start) output: chary char! char 2 win Rust Counters default: Win Useful EXAMPLES of Verilog HDL for Lab 5 and Lab 6 module stmachine(zmoore,x,reset, x,reset,clk; input output zmoore; zstate; sevenseg; output[1:0] output[6:0] reg [1:0] reg reg[6:0] parameter zmoore; sevenseg; always@(x or current_state) begin case(current_state) s0 : begin current_state,next_state; $1 s3 zmoore<=1; s3: begin end sevenseg<=7'b1111110; if(x==1) next_state<=s1; else next_state<=s3; end s1: begin zmoore<=1; sevenseg<=7'b0110000; if(x==1) next_state<=s2; else next_state<=s0; end $2: begin zmoore<=1; endcase end so if(reset) else sevenseg<=7'b1101101; if(x==1) next_state<=s3; else next_state<=s1; end zmoore<=0; = 2'b01, = 2'b11; // the control logic of the machine sevenseg<=7'b1111001; if(x==1) next_state<=s0; else next_state<=s2; end clk,zstate, sevenseg); //example of a state machine coded in Verilog // optional, will indicate which "state" the state machine is presently in always@(posedge clk or posedge reset) begin // the register part of the machine current_state<=s0; current_state<=next_state; assign zstate = current_state; endmodule = 2'b00, // internal signals for the state machine... but not outputs // zmoore is one of the desired outputs $2 = 2'b10,