Question on digital cmos vlsi design. Solve step by step in detail. Design an AOI21 compound logic gate using complementary CMOS topology. (AOI21 ( = overline{ mathrm{AB}+ mathrm{C}}) ). Choose the design with the least parasitic capacitance.

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Question on digital cmos vlsi design. Solve step by step in detail.   Design an AOI21 compound logic gate using complementary CMOS topology. (AOI21  ( = overline{ mathrm{AB}+ mathrm{C}})  ). Choose the design with the least parasitic capacitance.

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