(Solved):   QUESTION 3: The diff-amp configuration shown in Figure 11.7 is biased at 4 V and -4 V. The ...

 

QUESTION 3: The diff-amp configuration shown in Figure 11.7 is biased at 4 V and -4 V. The maximum power dissipation in the entire circuit is to be no more than 1.2 mW when v? = ? = 0. ¹1 The available transistors have parameters: B=90, VBE(on) = 0.61 V, and VA=00. Design the circuit to produce the maximum possible differential-mode voltage gain, but such that the common-mode input voltage can be within the range - 0.99< VCM 0.99 V and the transistors are still biased in the forward-active region. What is the value of A? R? (kQ) Format: 74.8945 Rc (kn) Format: 60.5838 8m (mA/V) Format : 8.9575 Ad Format: 29.45 V+ 1?R? 1cRc Ic?Rc V?0- ICA Activ Go to 23 T V- Figure 11.7 -01/2