Figure P10.32a gives the timing diagram of a microprocessor during a write cycle. Figure P10.32b gives the timing diagram of a memory-mapped peripheral during a write cycle. Using the timing information in Table P10.32, verify that the interface of Figure P10.32 will function correctly. Note that a memory-mapped peripheral is a peripheral that look

Question

Figure P10.32a gives the timing diagram of a microprocessor during a write cycle. Figure P10.32b gives the timing diagram of a memory-mapped peripheral during a write cycle. Using the timing information in Table P10.32, verify that the interface of Figure P10.32 will function correctly. Note that a memory-mapped peripheral is a peripheral that looks exactly like a block of static RAM as far as the processor is concerned (we cover such peripherals in Chapter 12). In this question, active-low signals are indicated by an asterisk rather than an overbar; for example, W* indicates NOT write.

TABLE P10.32

(a) Processor timing
(b) Peripheral timing

Figure P10.32

(a) Processor timing diagram
(b) Peripheral timing diagram
(c) Circuit of the CPU to peripheral interface

Note:

student submitted image, transcription available below = Address strobe (low when address from CPU valid)

student submitted image, transcription available below = Data strobe (low when data from CPU valid)

student submitted image, transcription available below = Read/not write (high in read cycle, low in write cycle)

student submitted image, transcription available below = Chip select (low when peripheral to take place in a read or write cycle)

student submitted image, transcription available below = Write enable (low when peripheral to take place in a write cycle)

\begin{tabular}{llll} Parameter & Name & Min & Max \\

t_{1}

& Address setup &

10 ns

& \\

t_{2}

& Address hold &

15 ns

& \\

t_{3}

& Address strobe asserted &

100 ns

& \\

t_{4}

& Address strobe low to &

20 ns

& \\ &

data strobe low & & \\

t_{5}

& Address strobe low to &

20 ns

&

30 ns

\\ &

R / \overline{W}

low & & \\

t_{6}

& Address strobe high to &

0 ns

&

10 ns

\\ &

R / \overline{W}

high & & \\

t_{7}

& Data setup time &

5 ns

&

10 ns

\\

t_{8}

& Data hold time & &

5 ns

\\ \hline \end{tabular}

\overline{AS}

\overline{CS}

\overline{WE}

R / \overline{W}

\overline{DS}

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