(Solved): Draw a pipeline diagram illustrating how the following assembly sequence would execute on a fully b ...

Draw a pipeline diagram illustrating how the following assembly sequence would execute on a fully bypassed pipelined TinyRV1 processor that uses hardware speculation which always predicts not-taken. Unlike the "standard" TinyRV1 processor, you should also assume that we add a single-instruction branch delay slot to the instruction set. So this processor will partially expose the control hazard in the instruction, but also use hardware speculation. Include microarchitectural dependency arrows to illustrate both data and control flow. addi $x1,x2,1$ bne $x0,x3$, foo \# assume $R[\mathrm{rs}]!=0$ addi $\mathrm{x}4,\mathrm{x}5,1$ \# instruction is in branch delay slot addi $x6,x7,1$ $\dots$ . add $\mathrm{x}8,\mathrm{x}1,\mathrm{x}4$ addi $\mathrm{x}9,\mathrm{x}1,1$ addi $\mathrm{x}1,\mathrm{x}2,1$ bne $x0,x3$, foo \# assume $R[rs]!=0$ addi $\mathrm{x}4,\mathrm{x}5,1$ \# instruction is in branch delay slot addi $\mathrm{x}6,\mathrm{x}7,1$ ... foo: add $x8,x1,x4$ addi $x9,x1,1$