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(Solved): Consider the C2MOS positive edge triggered register shown below: Note: Clearly mention the assumpti ...
Note: Clearly mention the assumptions considered for solving this problem.
1. Explain its operation by truth table
|
CLK |
D |
Xn+1Xn+1? |
Qn-1Qn-1? |
|
0 |
0 |
||
|
0 |
1 |
||
|
1 |
0 |
||
|
1 |
1 |
2. Why do you think there is no race condition even if there is overlap? 3. Show the simulation results for the case givxxxcen below.
Note: Be sure to take all necessary assumptions.
Master Stage Slave Stage
Expert Answer
1. clk D Xn+1 Qn-1 0 0 1 1 0 1 0 0 1 0 0 1 1 1 0 1 2. MASTER STAGE: when clk is high both M3,M4 transistors OFF state in Master stage, D=1 then M2 is