(Solved): 9/5.51 Draw the state diagram of the machine described by the Verilog model given below. module Pr ...

9/5.51 Draw the state diagram of the machine described by the Verilog model given below. module Prob_5_51 (output reg y_out, input x_in, clk, reset); parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10, s3 = 2'b11; reg [1:0] state, next_state; always @ (posedge clk, negedge reset) begin if (reset == 1'b0) state <= s0; else state <= next_state; always @(state, x_in) begin y_out= = 0; next_state = s0; case (state) s0: if x_in= 1 begin y_out = 0; if (x_in) next_state = s1; else next_state = s0; end s1: if x_in= 1 begin y_out = 0; if (x_in) next_state = s2; else next_state = s1; end s2: if x_in= 1 begin y_out = 1; if (x_in) next_state = s3; else next_state = s2; end s3: if x_in= 1 begin y_out = 1; if (x_in) next_state = s0; else next_state = s3; end default: next_state = s0; endcase end endmodule