(Solved): 14. Consider the following module template of a D type fip-flop: module D_FF (clk, d, q, clear): ir ...

14. Consider the following module template of a D type fip-flop: module D_FF (clk, d, q, clear): irput clk, a, elear: output q: \( r \operatorname{g} \) q: alvays \( Q \) (posedge clk, negedge clear) bogin if (lclear) else \( q \Leftrightarrow 0 \); else \( q \) end This module template describes A D.FF with a synchronous, active high clear A D-FF with a synchronous, active-low clear A D-FF with an asynchronons, active-high clear A D-FF with an asynchronous, active-low dear 15. Which of the following can tell you which modules are instantiated inside other modules? A timing diagram The component library The testbench The design hierarchy 16. RTL coding refers to modules written in which level of abatration? gate level dataflow behavioral all of the above dataflow and behavioral only