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(Solved): 10. Analyse the following VHDL sequential codes: (ULO library IEEE; use IEEE.STD_LOGIC 1164 .ALL; u ...
10. Analyse the following VHDL sequential codes: (ULO library IEEE; use IEEE.STD_LOGIC 1164 .ALL; use IEEE. NUMERIC_STD.ALL; entity dummy is end dummy; architecture sig of dummy is signal sum: integer := 0 ; signal sig1: integer:= 1; signal sig2: integer:= 2; signal sig3: integer:= 3 ; begin process begin sigl <= sig2 + sig3; sig2 <= sigl; ; sum <= sig1+sig2 +sig 3 ; wait; end process; end sig; Deduce the resulting value of 'sum', 'sig1', 'sig2', and 'sig3' when simulated. Explain your answer. A. ; B. ; C. ; D. ;