(Solved): 1. A state diagram of mod-6 synchronous counter with arbitrary counting sequence is given in Fig. 1 ...

1. A state diagram of mod-6 synchronous counter with arbitrary counting sequence is given in Fig. 1. (a) Please design this synchronous by T Flip-flops. Your answer should show the truth table including present state, next state, and Flip-flop inputs (note: use don't care for the unused states (1) and (2)), the K-map, and the circuit. (20\%) (b) Please demonstrates the unused states (D) and (2) transiting to which states (note: the detail analyses should be given in your answer). (8\%) 2. Implement an asynchronous up-counter with counting sequence \( 0-8 \) by positive edgetriggered D Flip-flops with negative "clear" function (see Fig. 2) and some logic gates (if necessary). (12\%)