(Solved): 1.2 The leader follower JK flip-flop Construct a Leader Follower JK flip-flop from NAND gates only ...

1.2 The leader follower JK flip-flop Construct a Leader Follower JK flip-flop from NAND gates only and check its operation by running through the timing diagram in the preliminary work. A possible circuit is shown below where the RS latches are constructed from NAND gates. Also verify the operation of the JK flip-flops supplied on the logic tutor. You should use a debounced switch to provide the clock input. Why? By pulsing the $\mathrm{J}$ or $\mathrm{K}$ inputs (ie $0-1-0$ ) when the clock is high show your demonstrator how 1 's catching ${}^1$ can occur. Note: the above table does not include 1's catching.